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document version: 3 date: 2004/06/17 customer : dell / wistron product functional specification 12.1 inch wide xga color tft lcd module model name: b121ew01 v2 final specification note: this specification is subject to change w i thout notice. (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 1/25 www..net
contents 1.0 handling precautions ........................................................................................................... ............ 4 2.0 general description ........................................................................................................ .................... 5 2.1 display characteristics .................................................................................................... .................. 5 2.2 functional block diagram ................................................................................................... ............... 6 3.0 absolute maximum ratings ................................................................................................... ............ 7 4.0 optical characteristics .................................................................................................... ................... 8 5.0 signal interface ........................................................................................................... ........................ 9 5.1 connectors ................................................................................................................. ......................... 9 5.2 signal pin ................................................................................................................. ............................ 9 5.3 signal description ......................................................................................................... ................... 10 5.4 signal electrical characteristics .......................................................................................... ........... 10 5.5 signal for lamp connector .................................................................................................. ............. 1 1 6.0 pixel format image ......................................................................................................... .................. 12 7.0 parameter guide line for ccfl inverter ..................................................................................... ..... 12 8.0timingcontrol?????????????????????????????????????14 8.1 t i ming characteristics ..................................................................................................... ................ 14 8.2 t i ming definition .......................................................................................................... ..................... 14 9.0 pow e r consumption .......................................................................................................... ............... 15 10. pow e r on/off sequence ...................................................................................................... ........... 16 11.0 reliability /safety requirement ........................................................................................... .......... 17 12.0 outlinedraw ing???????????????????????????????????..18 13.0 edidrecord ?????????????????????????????????????20 14.0 label format ????????????????????????????????????..24 15.0 packing dimension??????????????????????????????????24 (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 2/25 www..net
ii record of revision version and date page old description n e w d e s c r i p t i o n r e m a r k v1. 2004/04/16 all first release na v2. 2004/06/07 20 edid ( pix clock = 75mhz ) v3. 2004/06/17 9 pin 18 = nc pin 18 = bist p i n a s s i g n m e n t modify 14 8.1 timing characteristics modify 8.1 timing characteristics modify for customer request 15 add note 2: if inverter with pwm mode that can define lamp min current is 2.5ma (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 3/25 www..net
1.0 handling precautions 1) do not press or scratch the surface harder than a hb pencil lead because the polarizers are very fragile and could be easily damaged. 2) be sure to turn off power supply when in serting or disconnecting from input connector. 3) wipe off water droplets or oil immediately. long c ontact with the droplets may cause discoloration or spots. 4) when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth. 5) since the panel is made of glass, it may br eak or crack if dropped or bumped on hard surface. 6) protect the module from static electricity and insure proper groundi ng when handling. static electricity may cause damage to the cmos gate array ic. 7) do not disassemble the module. 8) do not press the reflector s heet at the back of the module. 9) avoid damaging the tft module. do not press the c enter of the ccfl reflector when it was taken out from the packing container. instead, press at the edge of the ccfl reflector softly. 10) do not rotate or tilt the signal interface connec tor of the tft module when you insert or remove other connector into the signal interface connector. 11) do not twist or bend the tft module when installa tion of the tft module into an enclosure (notebook pc bezel, for example). it should be taken into c onsideration that no bending/twisting forces are applied to the tft module from outside when designing t he enclosure. otherwise the tft module may be damaged. 12) cold cathode fluorescent lamp in lcd contains a sma ll amount of mercury. please follow local regulations for disposal. 13) the lcd module cont ains a small amount of material that has no flammability grade, so it should be supplied by power complied with requirement s of lim ited power source (2.1 1, iec60950 or ul1950). 14) the ccfl in the lcd module is supplied with limi ted current circuit (2.4, iec60950 or ul1950). do not connect the ccfl in hazardous voltage circuit. (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 4/25 www..net
2.0 general description this specification applies to the 12.1 in ch wide color tft/lcd module b121ew01 v2 this module is designed for a display uni t of notebook style personal computer. the screen format is intended to support the xga ( 1280(h) x 800(v)) screen and 262k colors (rgb 6-bits data driver). all input signals are lvds interface compatible. this module does not contain an inverter card for backlight. 2 2 . . 1 1 d d i i s s p p l l a a y y c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s the following items are characteri stics summary on the table under 25 j condition: i t e m s u n i t s p e c i f i c a t i o n s screen diagonal [mm] 307.9(12.1" wide) active area [mm] 261.12(h) x163.2(v) pixels h x v 1280(x3) x 800 pixel pitch [mm] 0.204(per one triad) x 0.204 pixel arrangement r.g.b. vertical stripe display mode normally white typical white luminance(ccfl=6.0ma) [cd/m 2 ] 200 typ.(5 point avg ) contrast ratio 300 : 1 min r e s p o n s e t i m e [ m s e c ] 2 5 t y p . nominal input voltage vdd [volt] +3.3 typ. typical power consumption (vdd line + vcfl line) [watt] 5.0 watt (w/o inverter, all blac k pattern)@ lcm circuit 1.5 watt(typ.),b/ l input 3.5 watt(typ.) weight [grams] 305g typ. (w/o inverter) physical size [mm] 275.82(w) x 178(h) x 5.5(d) max. electrical interface r/g/b data , 2 sync, signals, clock (4 pairs lvds) , dsptmg support color native 262k colors ( rgb 6-bit data driver ) temperature range operating storage (shipping) [ o c] [ o c] 0 to +50 -40 to +60 (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 5/25 www..net
2 2 . . 2 2 f f u u n n c c t t i i o o n n a a l l b b l l o o c c k k d d i i a a g g r r a a m m the following diagram shows the functional blo ck of the 12.1 inches color tft/lcd module: t f t a rra y/ cel l vdd lcd c o n t r o lle r lc d dr i v e car d b a c k lig h t u n it 1280 x 3 x 800 gnd dc - d c co nv er t e r re f c i r c u i t y- d r i v e r x- d r i v e r rx i n 0 rx i n 1 rx i n 2 rx clk i n (4 pa ir s l v d s ) hi r o s e df1 9 k- 2 0 p- 1 h m a t i ng t y p e d f 19g - 20s- 1 c j s t bhsr- 0 2 vs- 1 m a t i n g t y p e sm 0 2 b- bhss- 1 - t b lam p c o n nect o r ( 2 p in ) (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 6/25 www..net
3.0 absolute maximum ratings absolute maximum ratings of the module is as following: i t e m s y m b o l m i n m a x u n i t c o n d i t i o n s logic/lcd drive voltage vdd -0.3 +4.0 [volt] input voltage of signal vin -0.3 vdd+0.3 [volt] ccfl current icfl - 7 [ma] rms ccfl ignition voltage vs - 1160(25 o c ) v r m s n o t e 1 operating temperature top 0 +50 [ o c ] n o t e 2 operating humidity hop 5 95 [%rh] note 2 storage temperature tst -40 +65 [ o c ] n o t e 3 storage humidity hst 5 95 [%rh] note 2 vibration 1.5 10-500 [g hz] shock 200 , 3 [g ms] half sine wave note 1 : duration = 50msec note 2 : maximum wet-bulb should be 39 j and no condensation. note 3 : dell s pec . wet bulb temperature chart twb=3 9 c operating range storage range (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 7/25 www..net
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 j condition: item unit conditions min. ty p. max. viewing angle [degree] [degree] horizontal (right) cr = 10 (left) 40 40 - - - - cr: contrast ratio [degree] [degree] vertical (upper) cr = 10 (lower) 20 40 - - - - u n i f o r m i t y 5 p o i n t s 1 . 2 5 u n i f o r m i t y 1 3 p o i n t s 1 . 6 contrast ratio 300 - response time [ m sec] r i s i n g - 1 0 1 5 [ m s e c ] f a l l i n g - 1 5 2 0 color / chromatic i ty r e d x 0.547 0 . 5 7 7 0 . 6 0 7 coordinates (cie) r e d y 0.308 0 . 3 3 8 0 . 3 6 8 g r e e n x 0.28 0 . 3 1 0 . 3 4 g r e e n y 0.514 0 . 5 4 4 0 . 5 7 4 b l u e x 0.152 0 . 1 5 8 0 . 1 8 8 b l u e y 0.094 0 . 1 2 4 0 . 1 5 4 w h i t e x 0.283 0 . 3 1 3 0 . 3 4 3 white y 0.299 0 . 3 2 9 0 . 3 5 9 white luminance ccfl 6.0ma [c d/m 2 ] 5 points average 180 2 0 0 - note 1: 5 points position (display area : 261.12mm x 163.2) 1 2 3 4 5 h/4 h/4 h/4 h/4 h w w/ 4 w/4 w/4 w/ 4 (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 8/25 www..net
note 2: 13 points position w/ 4 w w/ 4 h h/4 h/4 h/4 h/4 7 9 10 w/ 4 1 8 w/ 4 10 10 10 10 2 3 13 12 4 5 6 11 5.0 signal interface 5 5 . . 1 1 c c o o n n n n e e c c t t o o r r s s physical interface is described as for the connector on module. these connectors are capable of accommodating t he following signals and will be following components. connector name / designation for signal connector manufacturer hirose ty pe / part number df19k-20p-1h mating housing/part number df19g-20s-1c mating contact/part number df19-2830 scfa connector name / designation for lamp connector manufacturer js t ty pe / part number bhsr-02vs-1 mating ty pe / part number sm02b-bhss-1-tb 5 5 . . 2 2 s s i i g g n n a a l l p p i i n n pin# signal name pin# signal name 1 v d d 2 v d d 3 g n d 4 g n d 5 r x i n 0 - 6 r x i n 0 + 7 g n d 8 r x i n 1 - 9 r x i n 1 + 1 0 g n d 1 1 r x i n 2 - 1 2 r x i n 2 + 1 3 g n d 1 4 rx c l k i n - 1 5 r x c l k i n + 1 6 g n d 1 7 v edid 1 8 b i s t 1 9 c l k edid 2 0 data edid (c) copy right au optronics dec., 2003 all rights reserved. b121ew 01 v2 no reproduction and redistribution allow ed. 9/25 www..net
5 5 . . 3 3 s s i i g g n n a a l l d d e e s s c c r r i i p p t t i i o o n n the module uses a lvds receiver embedded in auo?s asic. lvds is a differential signal technology for lcd interface and high-speed data transfer device. signal name description rxin0-, rxin0+ lvds different ial data input(red0-red5, green0) rxin1-, rxin1+ lvds differentia l data input(green1-green5, blue0-blue1) rxin2-, rxin2+ lvds differential data i nput(blue2-blue5, hsync, vsync, dsptmg) rxclkin-, rxclkin0+ lvds differential clock input vdd +3.3v power supply g n d g r o u n d note : input signals shall be in low status when vdd is off. internal circuit of lvds inputs are as following. signal name description +re d 5 +re d 4 +re d 3 +re d 2 +re d 1 +re d 0 red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) red-pixel data red-pixel data each red pixel's brightness data consists of these 6 bits pixel data. + g reen 5 + g reen 4 + g reen 3 + g reen 2 + g reen 1 + g reen 0 green data 5 (msb) green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) green-pixel data green-pixel data each green pixel's brightness data consists of these 6 bits pixel data. +blue 5 +blue 4 +blue 3 +blue 2 +blue 1 +blue 0 blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) blue-pixel data blue-pixel data each blue pixel's brightness data consists of these 6 bits pixel data. -dtclk data clock the typical frequency is 65.0 mhz. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. dsptmg display timing this signal is strobed at the falling edge of -dtclk. when the signal is high, the pixel data shall be valid to be displayed. vsync vertical sy nc the signal is synchronized to -dtclk . hsync horizontal sy nc the signal is synchronized to -dtclk . note: output signals from any system shall be low or hi-z state when vdd is off. 5 5 . . 4 4 s s i i g g n n a a l l e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 10/2 5 www..net
input signals shall be in low status when vdd is off. it is recommended to refer the specifications of sn75lvds86dgg (texas instruments) in detail. signal electrical characteristics are as follows; p a r a m e t e r c o n d i t i o n m i n m a x u n i t vth differential input high voltage(vcm=+1.2v) 100 [mv] vtl differential input low voltage(vcm=+1.2v) -100 [mv] lvds macro ac characteristics are as follows: m i n . m a x . clock frequency (f) 20mhz 85mhz data setup time (tsu) 600ps data hold time (thd) 600ps thd tsu input clock input data t 5 5 . . 5 5 s s i i g g n n a a l l f f o o r r l l a a m m p p c c o o n n n n e e c c t t o o r r pin # signal name 1 lamp high voltage 2 lamp low voltage (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 11/2 5 www..net
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format. 7.0 parameter guide line for ccfl inverter parameter min dp-1 max units condition white luminance 5 points average 180 200 ? note 2 ccfl frequency(fcfl) 50 70 [khz] (ta=25 j ) note 3 ccfl ignition voltage(vs) 1400 ? ? note 4 ccfl voltage (reference) (vcfl) ? ? note 5 ccfl power consumption (pcfl) ? ? note 5 note 1 : dp-1 are auo recommended design points. *1 all of characteristics listed are measured under the condition using the auo test inverter. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and subs tandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safe ty circuit ver carefully. impedance of ccfl, for instance, becomes more than 1 [m ohm] when ccfl is damaged. (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 12/2 5 www..net
*4 generally, ccfl has some amount of delay time after applying start-up voltage. it is recommended to keep on applying start-up voltage for 1 [sec] until discharge. *5 the ccfl inverter operating frequency must be carefully chosen so that no interfering noise stripes on the screen were induced. *6 reducing ccfl current increases ccfl disc harge voltage and generally increases ccfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. note 2 : it should be employed the inverter, which has ?duty dimming?, if iccfl is less than 4ma. note 3 : the ccfl inverter operating frequency should be ca refully determined to avoid interference between inverter and tft lcd. note 4: the inverter open voltage should be designed lar ger than the lamp starting voltage at t=0 o c, otherwise backlight may be blinking for a moment after turning on or not be able to turn on. the open voltage should be measured after ballast capacitor. if an inverter has shutdown function it should keep its open voltage. for longer than 1 second even if lamp connector is open. note 5 : calculator value for reference (icflvcfl=pcfl) 8 timing control (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 13/2 5 www..net
8 8 . . 1 1 t t i i m m i i n n g g c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s this is the signal timing required at the input of the user connector . all of the interface signal timing should be sat i sf ied wit h the following specifications . parameter symbol min. typ. max. unit condition clock frequency 1/ t clock 6 2 6 8 . 9 8 3 m h z p e r i o d t v 803 816 864 ac t i v e t v d 800 800 800 vertic al section b l a n k i n g t v b 3 1 6 6 4 t line p e r i o d t h 1302 1408 1600 ac t i v e t h d 1280 1280 1280 horizontal section b l a n k i n g t h b 2 2 1 2 8 3 2 0 t clock end-frame checking period tef 2 t line de checking period tde 6400 t line 8 f r a m e s 8 8 . . 2 2 t t i i m m i i n n g g d d e e f f i i n n i i t t i i o o n n (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 14/2 5 www..net
9.0 power consumption input power specificat ions are as follows; sy mbol parameter min ty p max units condition module v d d l o g i c / l c d d r i v e voltage 3.0 3.3 3.6 [volt] load capacitance 20uf pdd vdd power 1.6 [watt] all blac k pattern pdd max vdd power max 1.7 [watt] max pattern note idd idd current 400 ma 64 grayscale pattern idd max idd current max 420 ma vertical stripe line pattern note v d d r p a l l o w a b l e logic/lcd drive ripple voltage 5 0 0 [ m v ] p-p v d d n s a l l o w a b l e logic/lcd drive ripple noise 1 0 0 [ m v ] p-p lamp i c f l c c f l c u r r e n t 3 . 0 (note 2) 6 . 0 7 . 0 [ m a ] rms (ta=25 j ) v c f l c c f l v o l t a g e (reference) 580 [volt] rms (ta=25 j ) p c f l c c f l p o w e r consumption 3.5 [watt] (ta=25 j ) total pow e r consumption 5.0 watt (w/o inverter, all black pattern)@ lcm circuit 1.5 watt(typ.),b/l input 3.5 watt(typ.) note 1 : vdd=3.3v note 2 : if inv e rter w i th pwm mode that can define lamp min current is 2.5 ma. (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 15/2 5 www..net
10. power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. sequence of power-on/off and signal-on/off 0.5ms ?? t1 ?? 10ms 0ms ?? t2 ?? 50ms 0ms ?? t3 ?? 50ms 500ms ?? t4 200ms ?? t5 200ms ?? t6 t4 t3 t2 t5 valid t1 0. 1vdd 0. 9vdd 0. 1vdd 0. 9vdd t6 power supply vdd lvds interface backlight on apply the lamp voltage within the lcd operating range. when the backlight turns on before the lcd operation or the lcd turns off before the backlight turns off, the display may momentarily become abnormal. (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 16/2 5 www..net
1 1 .0 reliability /safety requirement r r e e l l i i a a b b i i l l i i t t y y t t e e s s t t c c o o n n d d i i t t i i o o n n s s i t e m s r e q u i r e d c o n d i t i o n s operating life ? high temp. temp.= + 5 0 = -25 1 1 1 1 . . 2 2 s s a a f f e e t t y y ul60950 (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 17/2 5 www..net
12 . outline drawing (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 18/2 5 www..net
13 . edid record (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 19/2 5 www..net
(c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 20/2 5 b121ew01 v2 edid table a d d r ess function value value value no tes hex hex bin dec 00 header 00 00000000 0 01 ff 11111111 255 02 ff 11111111 255 03 ff 11111111 255 04 ff 11111111 255 05 ff 11111111 255 06 ff 11111111 255 07 00 00000000 0 08 ei sa manuf . code lsb 06 00000110 6 asci i dat a st ring: b121ew01 09 compressed asci i af 10101111 175 auo 0a product code 01 00000001 1 01(12b01) 0b h e x , l sb first 0c 00001100 12 12(12b01) 0c 32-bit ser # 00 00000000 0 unused 0d 00 00000000 0 0e 00 00000000 0 0f 00 00000000 0 10 week of manuf act u re 01 00000001 1 week 01 11 year of manuf act u re 0e 00001110 14 14(2004-1990= 14) 12 edid structure ver. 01 00000001 1 13 edi d revision # 01 00000001 1 14 video input def init ion 80 10000000 128 digit a l i nput 15 max h image size 1a 00011010 26 26. 112cm 16 max v image size 10 00010000 16 16. 32cm 17 display gamma 78 01111000 120 gamma 2. 2 18 feat ure support 0a 00001010 10 n o d p ms,active o ff,r gb co lo r 19 red/ green low bit s a5 10100101 165 1a blue/ w h it e low bit s 50 01010000 80 1b red x/ high bit s 93 10010011 147 rx= 0 . 577 1c red y 56 01010110 86 ry = 0 . 338 1d green x 4f 01001111 79 gx= 0 . 310 1e green y 8b 10001011 139 gy = 0 . 544 1f blue x 28 00101000 40 bx= 0 . 158 www..net
20 blue y 21 00100001 33 by = 0 . 130 21 white x 50 01010000 80 wx= 0 . 313 22 white y 54 01010100 84 wy = 0 . 329 23 est ablished t i ming 1 00 00000000 0 unused 24 est ablished t i ming 2 00 00000000 0 25 manuf act u rer' s t i ming 00 00000000 0 26 st andard t i ming #1 01 00000001 1 unused 27 01 00000001 1 28 st andard t i ming #2 01 00000001 1 29 01 00000001 1 2a st andard t i ming #3 01 00000001 1 2b 01 00000001 1 2c st andard t i ming #4 01 00000001 1 2d 01 00000001 1 2e st andard t i ming #5 01 00000001 1 2f 01 00000001 1 30 st andard t i ming #6 01 00000001 1 31 01 00000001 1 32 st andard t i ming #7 01 00000001 1 33 01 00000001 1 34 st andard t i ming #8 01 00000001 1 35 01 00000001 1 36 pixel clock/ 10, 000 (lsb) 4c 01001100 76 t i ming descript o r #1 37 pixel clock/ 10, 000 (msb) 1d 00011101 29 1280x800 @65. 27_mode: pixel clock= 75. 0mhz 38 horiz. act i ve pixels(low er 8 bit s ) 00 00000000 0 horiz act i ve= 1280 pixels 39 horiz. blanking (low er 8 bit s ) 80 10000000 128 horiz blanking= 128 pixels 3a horiz. act i ve pixels: h oriz. blanking (upper4: 4 bit s ) 50 01010000 80 3b 20 00100000 32 vert cal act i ve= 800 lines 3c 10 00010000 16 vert ical blanking= 16 lines 3d vert . act i ve pixels: v ert . blanking (upper4: 4 bit s ) 30 00110000 48 3e 15 00010101 21 horiz sy nc. of f s et = 21 pixels 3f 20 00100000 32 horiz sy nc. pulse widt h= 32 pixels 40 ve rt. sy n c . offse t =x x li nes, sy nc widt h= xx lines 44 01000100 68 ve rti sy n c . offse t = 4 lines, s y n c widt h= 4 lines 41 horz. ver. sy nc/ w idt h (upper 2 bit s ) 00 00000000 0 42 hori. i m age size (low er 8 bit s ) 05 00000101 5 hori image size = 261. 12 mm 43 vert . i m age size (low er 8 bit s ) a3 10100011 163 vert i image size = 163. 2mm 44 hori. i m age size : vert . i m age size (upper 4 bit s ) 10 00010000 16 (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 21/2 5 www..net
45 00 00000000 0 horizont al border = 0 46 00 00000000 0 vert ical border = 0 47 18 00011000 24 48 det a iled t i ming/ monit o r 00 00000000 0 apple def init ion, see t he next sheet 49 descript o r #2 00 00000000 0 4a 00 00000000 0 4b 0f 00001111 15 4c version 00 00000000 0 4d value = hspw min /2 (pixel c l k s ) 00 00000000 0 de mode 4e value = hspw max /2 (pixel c l k s 00 00000000 0 de mode 4f value = t hbp min /2 (pixel c l k s ) 00 00000000 0 de mode 50 value = t hbp max /2 (pixel c l k s ) 00 00000000 0 de mode 51 value = vspw min /2 (line puls e s ) 00 00000000 0 de mode 52 value = vspw max /2 (line puls e s ) 00 00000000 0 de mode 53 value = t v bp min /2 (line puls e s 00 00000000 0 de mode 54 value = t v bp max /2 (line puls e s 00 00000000 0 de mode 55 th p min = value*2 + ha pix e l clks (pix el clks) 0b 00001011 11 1302= value*2+ 1280 56 th p max = value*2 + ha pix e l clks (pixel c l k s ) d2 11010010 210 1700= value*2+ 1280 57 tv p min = value*2 + va lines (line pulses) 02 00000010 2 803= value*2+ 800 58 tv p max = value*2 + va lines (line pulses) 10 00010000 16 832= value*2+ 800 59 00 00000000 0 5a det a iled t i ming/ monit o r 00 00000000 0 5b descript o r #3 00 00000000 0 5c 00 00000000 0 5d fe 11111110 254 5e 00 00000000 0 5f dell p/ n 1st charact e r 44 01000100 68 d 60 dell p/ n 2nd charact e r 35 00110101 53 5 61 dell p/ n 3rd charact e r 34 00110100 52 4 62 dell p/ n 4t h charact e r 30 00110000 48 0 63 dell p/ n 5t h charact e r 34 00110100 52 4 64 lcd supplier eedi d revision 00 00000000 0 65 manuf act u rer p/ n 42 01000010 66 b 66 manuf act u rer p/ n 31 00110001 49 1 67 manuf act u rer p/ n 32 00110010 50 2 68 manuf act u rer p/ n 31 00110001 49 1 (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 22/2 5 www..net
69 manuf act u rer p/ n 45 01000101 69 e 6a manuf act u rer p/ n 57 01010111 87 w 6b manuf act u rer p/ n 31 00110001 49 1 6c flag 00 00000000 0 6d flag 00 00000000 0 6e flag 00 00000000 0 6f d a ta ty p e ta g : asc ii strin g fe 11111110 254 70 flag 00 00000000 0 71 smbus= 15 nits e8 11101000 232 72 smbus= 21 nits e0 11100000 224 73 smbus= 30 nits c8 11001000 200 74 smbus= 40 nits b0 10110000 176 75 smbus= 60 nits 90 10010000 144 76 smbus= 90 nits 70 01110000 112 77 smbus=140 nits 50 01010000 80 78 smbus=max nits(typically = 00h) 00 00000000 0 79 01 00000001 1 7a 0a 00001010 10 7b 20 00100000 32 7c 20 00100000 32 7d 20 00100000 32 7e ext ension flag 00 00000000 0 7f checksum a9 10101001 169 6457 6626 14. label format (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 23/2 5 www..net
15.0 packing dimension 20pcs lcd module 12.1? lcd module carton carton label position esd bag (c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 24/2 5 www..net
(c) copy right au opt r onics dec. , 2003 all right s reserved. b121ew01 v2 no reproduct i on and redist ribut ion allow ed. 25/2 5 www..net

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